Principal ASIC Design Engineer RTL / Microarchitecture / High-Performance Networking Overview Seeking a Principal ASIC Design Engineer to own front-end design for complex, high-performance silicon used in advanced networking and AI infrastructure. This role will work closely with architecture, verification, emulation, DFT, and physical design teams to translate product requirements into robust microarchitecture and production-ready RTL. The ideal candidate is a hands-on technical leader with deep RTL design experience, multiple successful tapeouts, and a strong understanding of performance, power, area, timing, and design quality. Key Responsibilities Define microarchitecture and implement synthesizable RTL for complex ASIC blocks and subsystems. Develop high-quality SystemVerilog designs optimized for performance, power, area, and timing. Partner with Design Verification and Emulation teams on test strategy, debug, coverage closure, and design intent. Work with Physical Design and DFT teams on synthesis, timing closure, area optimization, clocking, and test logic integration. Review design reports, identify architectural or RTL bottlenecks, and drive fixes through tapeout and silicon bring-up. Required Qualifications 5+ years of ASIC or SoC logic design experience with strong hands-on RTL development. Strong SystemVerilog experience and solid understanding of digital design fundamentals, CDC, synthesis, timing, and clocking. Experience defining microarchitecture and developing complex ASIC blocks from specification through implementation. Ability to debug cross-functional issues with Verification, Emulation, Physical Design, and DFT teams. BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. Preferred Qualifications 12+ years of relevant experience with multiple successful ASIC tapeouts. Experience with Lint, CDC, RDC, formal verification, synthesis, STA, and front-end design methodology. Strong scripting skills using Python, Perl, Tcl, or similar languages. Experience analyzing timing, power, and area reports and making RTL or architectural changes to improve PPA. Exposure to silicon bring-up and post-silicon debug. Experience with high-performance networking ASICs, Ethernet switch silicon, packet processing, low-latency datapaths, NoC, SerDes integration, or AI infrastructure silicon. Background in switch ASICs, NICs, DPUs, network processors, or data center networking is a strong plus.

Estimated Min Rate :

$250000.00/

Annually Estimated Max Rate :

$265000.00/Annually What's In It for You? We welcome you to be a part of the largest and legendary global staffing companies to meet your career aspirations. Yoh's network of client companies has been employing professionals like you for over 65 years in the U.S., UK and Canada. Join Yoh's extensive talent community that will provide you with access to Yoh's vast network of opportunities and gain access to this exclusive opportunity available to you. Benefit eligibility is in accordance with applicable laws and client requirements.

Benefits include:

Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week) Health Savings Account (HSA) (for employees working 20+ hours per week) Life & Disability Insurance (for employees working 20+ hours per week) MetLife Voluntary Benefits Employee Assistance Program (EAP) 401K Retirement Savings Plan Direct Deposit & weekly epayroll Referral Bonus Programs Certification and training opportunities

Note:

Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply. Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

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