Senior Design for Test (DFT) Engineer

Job Title :

Senior DFT Engineer Location :

Santa Clara, CA Experience :

4+ Years in

DFT Skill:

[

ATPG , MBIST, IO

Test, Clock Verification] Job Summary We are seeking an experienced Senior

DFT / ATPG

Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as

MBIST, IO

Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with NVIDIA s crossfunctional teams to enable firsttimeright silicon and highquality products. Key Responsibilities Architect, implement, and validate DFT solutions to improve controllability and observability in complex GPU/SoC designs Lead scan-based DFT implementation, including scan insertion, compression, and test logic integration Develop and debug ATPG patterns targeting stuckat, transition, and additional fault models Implement and support MBIST architectures for onchip memory test, diagnosis, and coverage improvement Perform IO Test planning and validation to ensure reliable interface and pinlevel testing Support clock DFT and clock verification, including clock controllability, observability, and atspeed test enablement Analyze fault coverage reports and drive improvements while balancing power, performance, and area constraints Collaborate closely with RTL, physical design, verification, and product engineering teams Support pattern simulation, silicon bringup, manufacturing test debug, and yield ramp Perform root cause analysis for test escapes and manufacturing failures Document DFT methodologies, test strategies, and best practices aligned with NVIDIA quality standards