Senior DFT Engineer

Key Responsibilities Architect, implement, and validate DFT solutions to improve controllability and observability in complex GPU/SoC designs Lead scan-based DFT implementation , including scan insertion, compression, and test logic integration Develop and debug ATPG patterns targeting stuck‑at, transition, and additional fault models Implement and support MBIST architectures for on‑chip memory test, diagnosis, and coverage improvement Perform IO Test planning and validation to ensure reliable interface and pin‑level testing Support clock DFT and clock verification , including clock controllability, observability, and at‑speed test enablement Analyze fault coverage reports and drive improvements while balancing power, performance, and area constraints Collaborate closely with RTL, physical design, verification, and product engineering teams Support pattern simulation, silicon bring‑up, manufacturing test debug, and yield ramp Perform root cause analysis for test escapes and manufacturing failures Document DFT methodologies, test strategies, and best practices aligned with NVIDIA quality standards. Required Skills & Qualifications 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST , including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin‑level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals Experience with industry‑standard

DFT/ATPG EDA

tools Ability to work effectively in fast‑paced, high‑performance semiconductor programs Strong analytical, problem‑solving, and communication skills. Preferred Qualifications B-Tech , BE or equivalent degree in Electronics domain. Experience with silicon bring-up and production test support Exposure to advanced nodes and complex SoC & GPU architectures Exposure to low‑power and performance‑aware DFT techniques Experience supporting high‑volume production and yield optimization Knowledge of low-power and performance-aware DFT techniques Experience working in high-volume manufacturing environments