Job title: ASIC Design Engineer, RTL (Senior/Staff/Principal)

Location:

San Jose, CA or Colorado Springs, CO (on-site)

Salary:

$280k-580k total compHelp design the chips that move the world's AI data.

Every AI model trained in a hyperscale data center depends on silicon that moves huge amounts of data between processors, memory and storage, with no room for delay. We design that silicon. We're looking for experienced RTL designers to own key blocks of our next generation of high-performance ASICs, from the first spec review through bring-up in the lab.

You won't be one small part of a huge org. Your designs will ship in products running in some of the largest data centers on the planet.

What you'll own

• Microarchitecture:

  Turn architecture specs into detailed microarchitecture and clear design documents, and defend your choices in design reviews
• RTL design: Write clean, high-performance Verilog/SystemVerilog for complex logic. That includes pipelined datapaths, clock domain crossings, multi-clock and multi-power-domain designs, and low-power techniques

• Integration:

  Bring third-party IP into your blocks and make sure it works smoothly with the rest of the chip
• Meeting PPA targets: Push designs through timing closure and tune for power, performance and area

• Debug:

  Track down and fix hard design issues at every stage, from simulation and emulation through post-silicon
• Lab work: Take part in silicon bring-up and validation, and see your design come to life
• Cross-team work: Work day to day with verification, firmware, software, emulation and validation engineers across the full ASIC lifecycle.

What you bring

• A strong track record in digital IC design on ASICs or complex SoCs
• Deep, hands-on Verilog and/or SystemVerilog RTL experience
• Strong microarchitecture skills and sound RTL design methods
• Proven experience taking designs through timing closure
• The persistence and analytical skill to solve hard problems
• Comfort working in a fast-moving, highly technical team where you have real ownershipBonus points
• Experience with high-speed interconnect protocols such as PCIe or CXL
• Knowledge of AMBA buses (AXI, AHB, APB
• Background in switching or fabric architectures
• Experience with high-throughput data movement or storage systemsWhy engineers join this team
• Your work matters: The chips you design help power the world's AI and cloud infrastructure
• Hard problems: Performance, scale and power targets that push what silicon can do
• Room to grow: You'll work across architecture, RTL, bring-up and validation instead of being boxed into one narrow area
• Strong colleagues: You'll work with some of the most experienced engineers in the industry
• A real career path: Clear technical growth from Senior to Staff to Principal and beyond.

COMPENSATIONSenior:

$120k

• 160k base, 20% bonus, RSUs
• up to ~$280k total comp

Staff:

$150k

• 190k base, 25% bonus, RSUs
• up to ~$400k total comp

Principal:

$180k

• 240k base, 30% bonus, RSUs
• up to ~$580k total compIf you want to do the best RTL work of your career on chips that matter, we'd love to talk.

BenefitsHealth, dental, and vision insuranceLife and disability insuranceFSA and HSA401k with 6% matchESPPFlexible/Unlimited PTOAnnual bonus from 15-30% (depending on your level)VERY generous stocks!