Principal ASIC Design Engineer

Principal ASIC Design Engineer ForwardEdge

ASIC LLC

Saint Paul, MN Job Details Full-time $200,000 - $220,000 a year 15 hours ago Benefits Health insurance 401(k) Paid time off 401(k) matching Qualifications Team leadership

Full Job Description Position Description:

At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of

ASIC/FPGA

experience and more than 300 patents. Job Summary We are currently seeking a Principal ASIC Design Engineer responsible for developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will be planning, architecting and developing digital systems for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced architects, engineers and systems experts across the company. You will work closely with verification, analog design, physical design and architecture teams. Key Responsibilities Providing leadership to architects to understand the function and requirements for all types of digital systems, sub-systems, and design blocks. Working with architects, systems experts and analog engineers to understand and document digital/analog interactions as related to digital systems and sub-systems. Writing detailed implementation plans and specifications for complex digital systems, sub-systems and design blocks. Writing Register Transfer Level (RTL) code using industry standard hardware description languages. Writing test plans and coordinating with the Design Verification team to fully verify digital systems, sub-systems and design blocks. Synthesizing RTL code using industry standard tools and analyzing results. Providing RTL updates to meet Power, Performance and Area (PPA) requirements. Provide leadership, write and execute plans for the post silicon lab validation at the system and sub-system levels. Providing continued support for digital systems, sub-systems and design blocks working within a larger system level environment through productization and production. Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl). Provide digital leadership, expertise and guidance across design groups.

Qualifications:

Bachelor's or master's degree in electrical or computer engineering. Relevant prior experience working at this level as a Principal ASIC Design Engineer. Experience in Synthesis, linting, clock domain crossing tools Experience with RTL coding languages and industry common scripting languages. Experience with embedded digital systems and sub-systems. Excellent communication and technical leadership skills.

What We Offer Work-Life Balance:

Flexible 9/80 work schedule with every other Friday off

Competitive Comp & Benefits:

Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and

PTO Incentives:

Eligibility for short-term and long-term incentive programs Join ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world.