Principal Foundry Technologist

Compile and analyze data using common statistical techniques and effectively present key results along with recommended actions; practice continuous improvement and yield optimization and analyze products to ensure manufacturability and data sheet compliance Understand architecture and system requirements and provide sound technical assessment Define and design engineering structure in testchip for technology interception and enablement including data collection, analysis and model-silicon characterization. Provide comprehensive Power, Performance, Area and Cost analysis for technology enablement. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 8 + years of experience in semiconductor process development and manufacturing. 5+ years of experience in technology evaluation, testchip and modeling Deep understanding of device physics, foundry design collateral management, process qualification, broad fabrication process experience, device reliability, statistical analysis, yield improvement, and physical failure analysis techniques Experience in supporting design teams with PDKs, IP development, tapeout, establishing DFM and design for reliability requirements and implementation of test structures for test chips Product yield/performance analysis, and design process co-optimization. Familiarity with device-level measurements and associated test equipment, data analysis, modeling, simulation, targeting and projection Model based problem solving skills through data analysis and understanding of SOC design features, fab process interactions and test methodology. Knowledge of EDA tools from Cadence, Caliber, Synopsys, Siemens for device and IP study. Experience in leading cross functional teams and program/project management. Probability and statistics background including DOE's. Experience in product and test engineering, and ATE test program methodologies Knowledge in digital design floor planning, STA; taking RTL to GDS and optimize for PPA Some experience in coding using various languages including but not limited to Python, Java and C++; Leveraging and designing/optimizing AI/ML; DFT and DFM techniques