Job Title:

Layout/Mask Designer 5

Duration:

2 months (Possibility of extension based on business needs)

Location:

Folsom, CA, 95630

Job Summary:

Develops and implements physical design solutions for System-on-Chip (SoC) devices from RTL, netlists, and design constraints provided by engineering teams. Work may be completed through the use of EDA tools, automation scripts, and other computerized design equipment. Performs floorplanning, power grid design, placement, clock tree synthesis, routing, timing closure, and physical verification. Analyzes design quality, identifies implementation issues, and verifies completed layouts meet performance, power, area, and manufacturability requirements. May review physical design methodologies, validate implementation flows, and support tapeout activities.

Experience Required:

Requires 10+ years of experience.