We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

Locations:

Irvine, CA or San Jose, CA What You Will Do:

Define architecture, specifications, and circuit topologies for next-generation SerDes Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting Design high-performance analog/mixed-signal circuits in advanced node technologies Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring:

Masters degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design Proven record of taking high-speed SerDes design to tape-out and volume production Experience in lab bring-up, characterization, and debugging designs that reach out production Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes) Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs Strong communication and documentation skills