R&D Engineering, Sr Architect

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building EDA software that has to hold up under real-world custom IC design pressure, the kind where a layout decision at 3nm can make or break a tape-out schedule. You know that the difference between a tool designers trust and one they route around is usually in the details, the algorithm that shaves two hours off a placement run, the infrastructure decision that makes GAA process nodes actually usable instead of theoretically possible. You think in systems, not just features. When someone asks for a new routing capability, you are already mapping the impact on existing flows, the training burden on designers, and the maintenance cost three releases from now. You have used Custom Compiler or Virtuoso enough to know where the pain points live, and you care about solving them at the architecture level, not patching them at the UI level. You are comfortable setting direction for junior engineers while still writing code yourself. You do not need a perfect spec to get started. You talk to IP teams, understand what 2nm and 14A nodes actually demand, and build tools that make their jobs easier. At Synopsys, you will work on the platform that powers custom IC design across the industry, and what you architect will ship to customers building the next generation of chips. What You'll Be Doing Architect and develop placement and routing infrastructure for Custom Compiler targeting advanced GAA and FinFET process nodes including 5nm, 3nm, 2nm, and 14A Design and implement layout automation features that directly improve designer productivity in circuit layout for cutting-edge process technologies Set technical direction and operational specifications for Custom Compiler software based on analysis of customer workflows and EDA ecosystem requirements Drive research and development of new algorithms and tools that address real bottlenecks in custom IC layout for advanced nodes Collaborate with Synopsys IP teams to integrate and proliferate Custom Compiler layout automation technologies across internal design flows Mentor and guide junior engineers on software architecture, coding standards, and quality practices specific to EDA tool development Manage maintenance and evolution of existing tool sets and infrastructure across product releases, balancing new feature development with stability The Impact You Will Have Enable designers to complete complex custom IC layouts for 3nm and below process nodes faster and with fewer iterations Reduce time-to-tapeout for Synopsys IP teams and external customers through smarter placement and routing automation Shape the technical roadmap for Custom Compiler, influencing how thousands of analog and custom designers work daily Accelerate adoption of advanced GAA and FinFET technologies by making them accessible through better EDA tooling Build infrastructure that scales across multiple process nodes and design styles, creating leverage for the entire Custom Compiler platform Improve designer productivity measurably through tools that handle the complexity of 2nm and 14A node constraints Strengthen Synopsys' position in the custom design EDA market by delivering capabilities competitors cannot match What You'll Need Bachelor's degree with a minimum of 15 years of related experience, or an advanced degree with a minimum of 13 years of related experience, in building EDA tools, with a deep focus on custom IC design automation. Hands-on experience with Custom Design platforms, specifically Synopsys Custom Compiler or Cadence Virtuoso, in a development or power-user capacity Strong expertise in placement and routing algorithms for analog, mixed-signal, or custom digital layouts Proven ability to architect software systems that balance performance, maintainability, and extensibility in complex EDA environments Direct experience working with advanced process nodes (7nm or below), understanding the layout constraints and design rules that matter at scale Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent with demonstrable EDA software architecture experience Experience working with semiconductor IP teams or custom IC design teams is a strong plus Who You Are You can explain a complex routing algorithm tradeoff to an IP designer in two sentences without losing the technical nuance You write code that other engineers can actually maintain, and you care about that as much as you care about the feature itself You push back when a feature request does not align with the architecture, and you do it with a better alternative in hand You are comfortable presenting technical direction to senior leadership and defending your choices with data, not just intuition You move between deep technical work and cross-functional collaboration without losing momentum, whether that is debugging a placement engine or aligning roadmaps with the IP team You treat maintenance and infrastructure work as seriously as new feature development because you know that is what keeps a platform alive The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG