RFIC Layout Engineer

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. Minimum requirement of a bachelors degree\nFinFet experience. Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.\nKnowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.\nSolid understanding of RC delay, electromigration, and coupling.\nUnderstanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE.\nHigh level proficiency in interpretation of

CALIBRE DRC, ERC, LVS

in FinFet Technology.\nKnowledge of CADENCE layout tools.\nExcellent communication skills.\nScripting skills in PERL or SKILL.