Verification Engineer

Verification EngineerPosition Overview We are seeking a Verification Engineer to develop and execute verification strategies for complex digital designs and SoC blocks. The role focuses on building robust SystemVerilog/UVM testbenches, creating directed and constrained-random tests, automating verification flows with scripting, and collaborating with RTL designers and integration teams to ensure silicon quality and performance for protocols such as PCIe, CXL, NVMe, and SATA.Key ResponsibilitiesDesign, implement, and maintain verification environments and testbenches using SystemVerilog and UVM to validate RTL and SoC blocks.

Develop verification plans, create directed and constrained-random tests, and define coverage goals to drive sign-off criteria.

Create and integrate protocol VIPs and checkers for PCIe, CXL, NVMe, SATA and other interfaces; validate protocol compliance and interoperability.

Debug functional failures using simulators, waveform analysis, assertions, and root-cause analysis; work with RTL engineers to resolve issues.

Automate regression and verification flows using Python, Perl, and build/test frameworks; manage job submission, results collection, and metric reporting.

Collaborate with architects, RTL designers, firmware and software teams for system-level verification and bring-up activities, including FPGA/emu validation where applicable.

Develop test harnesses and C/C++/SystemC models as needed to accelerate verification and support co-verification with software.

Collect and analyze functional coverage and code coverage data, produce clear verification status reports, and recommend closure plans.

Contribute to verification methodology and infrastructure improvements, mentor junior engineers, and participate in design reviews.

QualificationsBachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.3+ years of industry experience in digital verification; experience may vary based on seniority level.

Strong proficiency in SystemVerilog and UVM for testbench development and constrained-random verification.

Hands-on experience with Verilog/RTL design and debug practices.

Proven experience with industry protocols: PCIe, CXL, NVMe, and/or SATA (protocol-level verification preferred).Solid scripting skills in Python and Perl for automation, plus familiarity with shell scripting and build systems.

Proficiency in C or C++ for verification models, test drivers, or co-simulation tasks.

Experience working on SoC verification, integration testing, and bringing up blocks in system contexts.

Familiarity with simulation tools, emulation, hardware bring-up, assertions (SVA/PSL), and coverage-driven methodologies.

Excellent problem-solving skills, strong written and verbal communication, and the ability to work effectively in cross-functional teams.

BenefitsMedicalDentalVisionPTOVIsion401kEquity Potential