DFT Engineers

DFT Engineers L&T Technology Services Limited. - 3.9 Santa Clara, CA Job Details Full-time 1 hour ago Qualifications Debugging Digital design

Full Job Description LTTS US Branch Santa Clara, California Job Description Job Description & Skill Requirement:

Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals Experience with industry standard

DFT/ATPG EDA

tools Ability to work effectively in fast paced, high performance semiconductor programs Strong analytical, problem solving, and communication skills

Qualification:

BE "LTTS is an Equal Opportunity Employer and maintains a clear policy against discrimination based on age, disability, sex, race, religion or belief, gender reassignment, marriage/civil partnership, pregnancy/maternity, or sexual orientation. As an inclusive organization, we actively endorse equal opportunities for all candidates with the right mix of talent, skills, and potential. We encourage applications from a diverse pool of candidates and selection for roles will solely be based on individual merit." "L&T Technology Services LTD is an equal opportunity employer and is committed to providing reasonable accommodations to qualified individuals with disabilities. If you require any accommodations to participate in the recruitment process or to perform the essential functions of the job, please let us know. We will work with you to provide reasonable accommodations in accordance with applicable law."

Job Requirement Job Description & Skill Requirement:

Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals Experience with industry standard

DFT/ATPG EDA

tools Ability to work effectively in fast paced, high performance semiconductor programs Strong analytical, problem solving, and communication skills

Qualification:

BE "LTTS is an Equal Opportunity Employer and maintains a clear policy against discrimination based on age, disability, sex, race, religion or belief, gender reassignment, marriage/civil partnership, pregnancy/maternity, or sexual orientation. As an inclusive organization, we actively endorse equal opportunities for all candidates with the right mix of talent, skills, and potential. We encourage applications from a diverse pool of candidates and selection for roles will solely be based on individual merit." "L&T Technology Services LTD is an equal opportunity employer and is committed to providing reasonable accommodations to qualified individuals with disabilities. If you require any accommodations to participate in the recruitment process or to perform the essential functions of the job, please let us know. We will work with you to provide reasonable accommodations in accordance with applicable law."