ASIC Formal Verification Engineer, TPU Compute

ASIC Formal Verification Engineer, TPU Compute corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in silicon development or ASIC/SoC design. Experience with SystemVerilog Assertions (SVA) and formal verification methods.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture. 10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips. Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal). Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking. Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers. Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA). About the job As an ASIC Formal Verification Engineer, you'll contribute formal verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators. The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about . Responsibilities Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques. Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects. Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans. Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics. Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.