Find & Apply For Verification Engineer Jobs in Sunnyvale, California

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent a decade or more in the trenches of Physical Verification, where a single misaligned rule deck can blow up a tapeout and where debugging a million DRC violations at 3nm means understanding both the tool and the physics underneath it. You know IC Validator, Calibre, or similar tools well enough to write runsets from scratch, debug them when they fail in ways the documentation never predicted, and explain to a frustrated design team why their custom cell is flagging errors that are actually correct. You are comfortable walking into a customer site where they are skeptical about switching tools, running a benchmark that proves the case, and then staying through deployment until their signoff flow is rock solid. You do not just answer questions, you ask better ones. When a customer says their LVS is failing, you dig into whether it is a netlist issue, a rule deck bug, or a layout assumption that broke three nodes ago. You are curious about what comes next. AI and agentic workflows are not buzzwords to you, they are tools you want to learn, apply, and help shape for an industry that desperately needs better automation. At Synopsys, you will work with customers who are building the most advanced chips in the world, and what you help them deploy will determine whether their tapeouts succeed or slip. What You'll Be Doing Drive IC Validator evaluations and competitive benchmarks at leading semiconductor customers, from initial setup through production signoff adoption Develop, customize, and debug Physical Verification rule decks and runsets for DRC, LVS, FILL, and PERC across advanced process nodes Solve complex customer issues that span tool behavior, runset logic, design methodology, and foundry rule interpretation Lead technical demonstrations, training sessions, and hands-on customer engagements that move evaluations to deployment Build and support AI/ML and agentic applications for Physical Verification, including intelligent debug, violation classification, and workflow automation Collaborate with R D, Product Engineering, and Sales to translate customer feedback into product requirements and enhancements Script and automate Physical Verification flows using Python, TCL, Perl, and shell scripting to improve customer productivity and adoption The Impact You Will Have Enable customers to tape out advanced-node designs on time by ensuring their Physical Verification flows are correct, efficient, and production-ready Accelerate IC Validator adoption at strategic accounts, directly contributing to Synopsys revenue and market position in Physical Verification Reduce customer debug time and engineering effort by deploying AI-assisted workflows that catch issues earlier and classify violations intelligently Influence the future of Synopsys Physical Verification tools by providing real-world customer feedback that shapes R D priorities Build long-term technical relationships with customers that make Synopsys their trusted partner for signoff verification Help define how AI and agentic technologies will transform Physical Verification workflows across the semiconductor industry Improve foundry rule deck quality and deployment speed by identifying gaps, debugging issues, and working with ecosystem partners What You'll Need Bachelor's or Master's degree in Electrical Engineering, Computer Science, VLSI, or a related technical field 10+ years of hands-on industry experience in Physical Verification, including DRC, LVS, FILL, and PERC methodologies Deep experience with Physical Verification tools such as IC Validator, Calibre, Assura, or equivalent EDA solutions Strong scripting and automation skills in Python, TCL, Perl, or shell scripting for runset development and workflow automation Proven ability to develop, qualify, and debug Physical Verification rule decks and runsets for complex designs Familiarity with Physical Design flows using Fusion Compiler or Innovus, and custom layout environments like Custom Compiler or Virtuoso Experience driving customer evaluations, competitive benchmarks, and production deployment at semiconductor companies is a strong plus Who You Are You can walk into a customer meeting where the design team is stuck on a failing LVS run, diagnose the issue in real time, and leave with a fix and a plan You are comfortable managing multiple customer engagements at once, prioritizing based on urgency and business impact without losing track of technical details You push back when a customer request does not make technical sense, and you do it in a way that builds trust rather than friction You are genuinely curious about AI and machine learning applications in EDA, even if you are still learning, and you want to be part of building that future You can explain a complex Physical Verification tradeoff to a customer VP in two sentences without losing the technical nuance that matters You do not wait for perfect information or complete documentation, you figure out what is missing, ask the right people, and move forward The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. #LI-CM1