Secret Cleared FPGA Verification Engineer (Job ID 003150)

Secret Cleared FPGA Verification Engineer (Job

ID 003150

) Innovien Solutions - 3.7 Sunnyvale, CA Job Details Permanent | Full-time | Contract From $80 an hour 14 hours ago Benefits Health savings account Health insurance Dental insurance 401(k) Flexible spending account Paid time off Vision insurance 401(k) matching Life insurance Referral program Retirement plan Qualifications Regression testing implementation Verification (System development task) Test case design FPGA Triage Analysis skills Test analysis SystemVerilog Debugging Failure analysis Full Job Description FPGA Verification Engineer | Active Secret Clearance Required Innovien is supporting a high-priority national defense program, and we're hiring an FPGA Verification Engineer to own the chip-level verification work. The test environment is built and the RTL is locked — you skip the setup and go straight to executing the cases that prove the chip behaves exactly as it has to. This is deep verification work on hardware that matters. What You'll Do Execute directed and constrained-random test cases and stimulus against completed

FPGA RTL

to verify chip-level functional behavior against design specifications Run functional simulations in an established VCS environment, analyze results, and debug failures using waveform analysis and coverage reports Identify, document, and drive failures to resolution alongside the RTL design team Re-run regression suites as design changes come through to confirm fixes hold and nothing downstream breaks Support verification across program assemblies through the build and verification phase What You Bring 6+ years of hands-on FPGA verification focused on functional verification — not RTL design or board bring-up Proven chip-level verification experience running against completed

RTL:

directed and constrained-random test cases, proving functional behavior against a design spec Strong working knowledge of UVM in SystemVerilog — able to build and run stimulus, triage failures, and close out verification problems independently Hands-on Synopsys VCS for functional simulation, testbench execution, and RTL debug; comfortable driving regressions and reading coverage reports Active U.S. Secret clearance; U.S. citizenship required Nice to Have Verdi for waveform analysis and debug alongside VCS; Vivado for Xilinx/AMD toolchain work Questa or ModelSim simulation experience Prior verification on defense, aerospace, or other cleared programs in a classified environment Familiarity with Lint and CDC analysis for code quality and clock domain crossing checks Details Active U.S. Secret clearance required

Pay:

From $80.00 per hour

Benefits:

401(k) 401(k) matching Dental insurance Flexible spending account Health insurance Health savings account Life insurance Paid time off Referral program Retirement plan Vision insurance

Work Location:

In person