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SCITRAVEL

Yes, 10% of the TimeDescriptionAt Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history

from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon.

We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Join Northrop Grumman Eastern Region Engineering Team on our continued mission to push the boundaries of possible across space systems. Enjoy a culture w your voice is valued and start contributing to our team of passionate professionals providing real-life solutions to our world's biggest challenges. We take pride in creating purposeful work and allowing our employees to grow and achieve their goals every day by Defining Possible. With our competitive pay and comprehensive benefits, we have the right opportunities to fit your life and launch your career today.

Northrop Grumman Space Systems is currently seeking a Staff FPGA Verification Engineer for the development of digital subsystems and products. In this position the Verification Engineer will be leading FPGA verification efforts across multiple programs. This individual will be responsible for defining, implementing and scaling a modern verification methodology using VUnit, while also providing technical leadership and team oversight. The ideal candidate brings deep expertise in FPGA verification, strong leadership skills and experience in aerospace/defense or other high-reliability environments.

Their primary task is to verify that FPGA designs meet the necessary specifications and operate as intended, identifying and correcting potential issues early in the design process. This role will work out of our Linthicum, MD campus.

Roles and Responsibilities:

Verification Planning Strategy
Create verification plans from system requirements, define scope, methodology, coding standards, coverage goals, and traceability matrices.
VUnit Framework Architecture
Design and roll out a reusable, VUnit-based verification environment, including libraries, VIP, and a modular test-bench architecture that can be shared across programs.
Automation CI/CD
Set up CI pipelines (e.g., Jenkins) for nightly regression, coverage collection, and metric reporting; automate test generation, execution, and result analysis with Python/Tcl scripts.
Test Development Execution
Write VHDL test benches and VUnit test suites; develop functional-coverage models, assertions, directed and random stimulus, and verification IP as needed.
Debug Failure Analysis
Perform root-cause analysis of simulation failures, coordinate hardware bring-up and lab validation, and work with designers to resolve bugs quickly.
Verification Closure
Deliver functional-coverage, code-coverage, and requirements-traceability reports; ensure all verification metrics meet program exit criteria before design hand-off.
Leadership Mentorship
Lead a team of FPGA verification engineers across multiple programs, coach junior staff on verification best practices, and promote design-for-verification (DFV) throughout the organization.
Cross-Team Collaboration
Partner with design, systems, firmware, and software groups to guarantee complete verification coverage; actively participate in SRR, PDR, CDR, and TRR reviews.
Risk Management Compliance
Identify technical risks early, define mitigation plans, and enforce adnce to internal FPGA development processes, security standards, and DoD clearance requirements.
Continuous Improvement
Drive adoption of industry-standard verification methodologies, evaluate emerging tools, and contribute to process-optimization initiatives that enhance productivity and product quality.

Basic Qualifications:

\nBachelor's degree with 12 years of experience, a master's degree with 10 years of experience or a PhD with 7 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.\n
\nProficiency in hardware description languages (e.g., SystemVerilog, Verilog, VHDL).\n
\nFamiliarity with industry-standard tools (e.g. Synopsys, Mentor Graphics).\n
\nKnowledge and hands-on experience with VUnit.\n
\nDigital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential\n
\nCandidate must have good communication skills, strong interpersonal skills, and good oral and written presentation skills\n
\nMust be able to mentor and coach early career Engineers as needed\n
\nMust be able to obtain and maintain Secret or Top-Secret level security clearance, per business requirements\n
\nExperience developing test plans, participating in reviews, test development and RTL debug\n
\nNo Clearance required to start but must have the ability to obtain and maintain a TS/SCI clearance w/SAP\n
\nU.

S. Citizenship required\n

Preferred Qualifications:

\nAdvanced Degree with at least 10 years of professional experience in related industry\n
\nActive DoD Top Secret Clearance or higher with SAP Access and or SCI eligibility\n
\nExperience with Verification IP integration and/or development\n
\nExperience with a coverage-driven verification methodology from planning through closure\n
\nExperience in creating comprehensive documentation of test cases, verification plans/methods, and test results for review and future reference.\n
\nDevelopment of scripts and use of verification tools like VUnit or proprietary frameworks to streamline and automate verification processes.\n
\nKnowledge of industry standard bus or I/O interfaces\n
\nExperience with VHDL Assertions\n
\n

FPGA/ASIC

design and/or development process experience\n

\nExperience with scripting languages (Python, Tcl, Makefile)\n
\nKnowledge of digital signal processing\n
\nKnowledge of working with Xilinx and MicroChip FPGAs (Kintex, Zynq ultrascale, RTG4, etc)\n
\nEffective communication with systems and software teams for requirements, ICDs, handoffs, etc.\n
\nAble to work effectively within a development team to understand system level inter-dependence and design constraints\n
\nActive Top Secret clearance a plus\n

Primary Level Salary Range:

$185,900.00

$278,900.

00\nThe above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.\nDepending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.\nThe application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.\nNorthrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://northropgrumman/EEO. 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FPGA Verification Engineer (Level 5)