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TechBiz Global GmbH
Coherency Verification Engineer
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Job Description
Job description At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Coherency Verification Engineer to join one of our clients' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.
Develop and maintain verification environments using SystemVerilog and UVM.Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.
Work on the verification of coherent systems, including cache-related functionality and interconnect behavior.
Validate designs involving CHI protocol, cache structures, coherency mechanisms, and system-level interactions.
Run and manage simulations, regressions, and debug failures using industry-standard verification tools.
Apply both formal and dynamic verification methodologies to identify design issues early.
Use scripting languages such as Python, Perl, Bash, or TCL to automate verification flows and regression processes.
Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.
Track, document, and communicate verification progress, bugs, coverage status, and technical risks.
Contribute to continuous improvement of verification methodology, tools, and best practices.
Master or PhDEnglish C1Industrial experience +8 yearsProficiency in SystemVerilog and UVMKnowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools Experience with simulation and simulation toolsKnowledge of revision control methodology and tools (git, svn)Experience in block level and sub-system or top level verificationExperience with formal and dynamic verificationStrong problem-solving skills and attention to detailExcellent communication and teamwork abilitiesKnowledge of the CHI protocolUnderstanding of caches' structure and parametersExperience in verification of coherent systems
Responsibilities:
Verify complex digital designs at RTL level according to architecture and design specifications.Develop and maintain verification environments using SystemVerilog and UVM.Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.
Work on the verification of coherent systems, including cache-related functionality and interconnect behavior.
Validate designs involving CHI protocol, cache structures, coherency mechanisms, and system-level interactions.
Run and manage simulations, regressions, and debug failures using industry-standard verification tools.
Apply both formal and dynamic verification methodologies to identify design issues early.
Use scripting languages such as Python, Perl, Bash, or TCL to automate verification flows and regression processes.
Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.
Track, document, and communicate verification progress, bugs, coverage status, and technical risks.
Contribute to continuous improvement of verification methodology, tools, and best practices.
Master or PhDEnglish C1Industrial experience +8 yearsProficiency in SystemVerilog and UVMKnowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools Experience with simulation and simulation toolsKnowledge of revision control methodology and tools (git, svn)Experience in block level and sub-system or top level verificationExperience with formal and dynamic verificationStrong problem-solving skills and attention to detailExcellent communication and teamwork abilitiesKnowledge of the CHI protocolUnderstanding of caches' structure and parametersExperience in verification of coherent systems
Benefits
- Dental Insurance