Hiring DFT Engineer || Hybrid at Santa Clara, CA || FTE/W2

Hi, Please check the below position and revert back with updated resume Immediate joiners will be preferred. Fulltime or W2 contract no C2C/C2

H Job Title:

DFT Engineer (Design for Test)

Experience:

5 12

Years Location:

Santa Clara, California Work Mode:

Hybrid / Work From Office - min 3days per week onsite Contract type: FTE/W2 contract (No C2C/C2H) Key Responsibilities Develop and implement DFT architecture for complex SoC and ASIC designs. Integrate and validate Scan, MBIST, LBIST, JTAG, Boundary Scan, and ATPG methodologies. Work closely with RTL, Physical Design, and Verification teams for testability closure. Generate and debug ATPG patterns for stuck-at and transition fault coverage. Perform DFT verification using simulation and formal validation techniques. Support silicon bring-up, diagnosis, and yield improvement activities. Drive test coverage optimization while balancing power, timing, and area constraints. Required Skills Hands-on experience with industry-standard DFT tools such as Synopsys Tessent / DFT Compiler / TetraMAX or equivalent. Strong understanding of scan insertion, compression, MBIST, and ATPG flows. Experience with SoC-level DFT integration and hierarchical DFT methodologies. Familiarity with Verilog/SystemVerilog and scripting languages such as TCL, Perl, or Python. Knowledge of advanced technology nodes and low-power DFT techniques is preferred. Strong debugging, analytical, and communication skills. Qualifications Bachelor's or Master's degree in Electronics / VLSI / Electrical Engineering.