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Analog Devices

Staff Engineer, Design Verification Engineering

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What they do

A Verification Engineer is responsible for ensuring that a product meets its specifications and requirements. Designs methods to test products, identify bugs in software products, and communicates with cross-functional teams, ensuring product development procedures and outcomes meets regulations. Primary objective is to verify that the system functions correctly and reliably according to its design and intended purpose.

$129,832 / year median in Massachusetts

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Job Description

Staff Engineer, Design Verification Engineering Analog Devices
  • 3.9 Wilmington, MA Job Details Full-time $171,787
  • $209,715 a year 18 hours ago Benefits Paid holidays Health insurance Dental insurance 401(k) Work from home Vision insurance Qualifications Integrated circuits (ICs) Test Case Documentation (Quality assurance practices) Electronics test plan development Verilog Simulation tools Test analysis Debugging Test Planning (Quality assurance practices) Full Job Description About Analog Devices Analog Devices, Inc.
(
NASDAQ:
ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in
FY25, ADI
ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .
Employer:
Analog Devices, Inc.
Job Title:
Staff Engineer, Design Verification Engineering Job Requisition:
1010.1263.5 / R264022
Job Location:
Wilmington, Massachusetts Job Type:
Full Time Rate of Pay:
$171,787
  • $209,715 per year
Duties:
Develop and execute UVM-based verification environments for block-level and full-chip
ASIC/SOC
designs. Create and implement verification plans and strategies, including constrained-random and directed test cases. Write and analyze functional coverage, assertions, and metrics to ensure thorough verification and track progress. Integrate and verify third-party and custom IPs/VIPs within subsystem-level UVM environments. Collaborate with design and cross-functional teams to review test plans, resolve issues, and ensure coverage closure. Support post-silicon verification activities, working with evaluation and applications engineering teams. Automate simulation data analysis and model validation using scripting languages and design automation tools. Partial telecommute benefit (2 days/week work from home).
Requirements:
Must have a Master's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing IC design or validation. In the alternative, a Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing IC design or validation. Must also possess the following (quantitative experience requirements not applicable to this section): Demonstrated Expertise ("DE") using metric-driven verification throughout the full lifecycle of design/verification, including verification planning, test bench and test case development using System Verilog and UVM. DE learning end application/systems and mapping into smart verification test plans. DE translating Design Verification requirements such as test plans into a robust DV environment as well as architecting and analyzing coverage to drive convergence. DE using UVM agents, and integrating third-party or custom Verification IPs (VIPs) to develop stimulus sequences and functional checkers within a UVM testbench. DE debugging simulations and analyzing waveforms.
Contact:
Eligible for employee referral program.
Apply online at https:
//www.analog.com/en/careers.html and
Reference Position Number:
R264022 . For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce
  • Bureau of Industry and Security and/or the U.S. Department of State
  • Directorate of Defense Trade Controls. As such, applicants for this position
  • except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3)
  • may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the
Law:
Notice of Applicant Rights Under the Law .
Job Req Type:
Experienced Required Travel:
No Shift Type:
1st Shift/Days Actual wage offered may vary depending on work location , experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.