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Design Verification Engineer | BCP

Job

Texas Instruments Incorporated

Knoxville, TN (In Person)

Full-Time

Posted 8 weeks ago (Updated 2 weeks ago) • Actively hiring

Expires 5/27/2026

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Job Description

Change the world. Love your job. The Battery Charging Products group at Texas Instruments is looking for a candidate that is interested in working in a challenging, fast-paced environment. As a digital design verification engineer, you will help verify new TI battery charger products and make our customers' visions a reality. You will help define, model, and simulate digital cores for battery management devices. We are looking for a self motivated, highly driven digital minded engineer to make an immediate impact on current developments, and help us grow market share in a competitive, constantly changing market. TI offers an extraordinary culture, competitive benefits, professional development opportunities and collaboration coupled with a social responsibility. A career at TI provides the chance to work with some of the world's most dynamic technologies that help people learn, grow, connect and discover. Some of your responsibilities will include: Verifying digital cores of battery charger ICs Collaborating with systems and analog engineers to define architecture of digital core Participating in design reviews and creating the necessary design and product documentation Supporting multiple projects concurrently Improving design verification methodology Creating verification plans from datasheets, input from systems engineers, and customer feedback Performing required simulations and analysis to ensure spec compliance and superior performance at a competitive cost Developing and maintaining simulation models for digital and analog blocks Evaluating device operation and performance in lab
Minimum Requirement:
B.S. in Electrical Engineering or related field 3+ years of relevant design verification experience
Preferred Qualifications:
RTL design, preferably Verilog/Systemverilog. Ability to robustly verify these implementations from a functional, formal, and timing standpoint. Experience with gate level netlist simulations. Experience with digital design tools (Cadence). Excellent self-organizing and time management skills. Knowledge of scripting and programming languages such as Python a plus. Knowledge of UVM a plus. Knowledge of VAMS and digital modeling a plus.

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