ASIC Engineer, Design Verification

Between $132k and $163k Per Year DOE (Depends on Experience) Position range in Travis County $73k - $126k Per Year ASIC Engineer, Design Verification Meta Platforms, Inc.

Occupation:

Industrial Engineers

Location:

Austin, TX - 78701 Positions available: 1 Job #: 16996998

Source:

WorkInTexas

Posted:

03/31/2026

Updated:

04/03/2026

Expires:

05/05/2026

Web Site:

WorkInTexas Onsite /

Remote:

Not Specified

Job Type:

Regular, Full Time (30 Hours or More), Permanent Employment, Day Shift

Agency Job ID:

REQ-2603-160416

Job Requirements and Properties Help for Job Requirements and Properties. Work Onsite Full Time Education Bachelor's Degree Experience 12 Month(s) Schedule Full Time Job Type Regular Duration Permanent Employment Hours 40 Hours Per Week Shift Day Shift Public Transit Available Benefits Help for .

Employer:

META PLATFORMS, INC.

(f/k/a Facebook, Inc.)

Job Title:

ASIC Engineer, Design Verification Job Code:

REQ-2603-160416

Job Location:

Austin, Texas Job Type:

Full-time, 9am - 6pm, 40 hours a week, Monday -

Friday Salary:

$132,198.00/year to $162,580.00/year + bonus + equity + benefits. Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus or equity or sales incentives, if applicable. In addition to base salary, Meta offers benefits. Learn more about benefits at Meta at this link: https://www.metacareers.com/benefits.

Duties:

Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Define and implement IP/SoC verification plans, build verifications test benches to block IP/subsystem/ SoC level verification and develop functional tests based Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality.

Requirements:

Requires a Bachelors degree (or foreign equivalent) in Computer Science, Computer Software, Computer Engineering, Electrical and Computer Engineering, Electronics and Telecommunication Engineering, Applied Sciences, Mathematics, Physics, or related field and 1 year of work experience in the job offered or in a computer-related occupation. Requires 1 year of experience in the following: Verilog, System Verilog/UVM methodology or C/C++ based verification; Block/IP/sub-system or SoC level verification based on SystemVerilog UVM/OVM based methodologies; EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments; Implementing Design Verification infrastructure (Testbench, RAL based register verification, Functional coverage, or Regression setup) and executing the full verification cycle; and Industry standard Bus Protocols, such as AMBA AXI, AHB, or APB.