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Qualcomm
Software Engineer — RISC-V Random Test Generator & Assembler Infrastructure
Career Insights for Engine and Machine Fabricator / Assembler
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What they do
An Engine and Machine Fabricator or Assembler constructs, assembles, or rebuilds machines, such as engines, turbines, and similar equipment used in such industries as construction, extraction, textiles, and paper manufacturing.
$52,844 / year median in California
+4% projected growth
Job Description
##
Company:
Qualcomm Technologies, Inc. ##Job Area:
Engineering Group, Engineering Group >CPU Engineering General Summary:
About the Role You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of aRISC-V CPU
design-verification toolchain. The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising theRVA23.1 ISA
— including privileged modes, virtual memory, interrupts, vector, and cryptography extensions. The assembler library provides the bit-accurate instruction encoding layer that the RTG and other tools consume. What You'll Do- Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.
- Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the
RISC-V ISA
spec.- Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
- Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
- Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers). What We're Looking For
- 2-5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
- Solid Python 3 skills; comfort with generator-based coroutines and object- oriented design patterns.
- Working knowledge of the
RISC-V ISA
instruction encoding formats (R/I/S/B/ U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model. Alternatively, similar knowledge for x86 or ARM.- Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
- Exposure to random test generation flows or ISS/RTL co-simulation is a plus. Nice to Have
- Compiler development experience.
- Understanding of hypervisor and/or
AIA/IMSIC
interrupt architecture.- Familiarity with constraint-propagation libraries.
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.