Staff Design Architect(Datapath), HBM

Req ID:

JR93488 Staff Design Architect(Datapath), HBM Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a highly motivated HBM Datapath Architect to architect, design, and optimize high‑speed data paths for next‑generation High Bandwidth Memory (HBM) products! This role focuses on logic‑die and core‑die datapath circuitry, enabling industry‑leading bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions. The ideal candidate will work closely with design, PHY, ECC, verification, layout, and system teams to deliver robust datapath designs from concept through silicon bring‑up and production. # Responsibilities will include, but are not limited to:

• Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic
• Develop high‑speed, low‑latency datapath circuits supporting multi‑channel HBM architectures and wide internal buses
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes
• Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms
• Collaborate with multi-functional teams to translate specifications into robust micro‑architectures
• Collaborate with PHY, DFT, verification, and layout teams to ensure accurate functionality, testability, and manufacturability
• Drive schematic‑level and RTL‑level datapath implementations, including clocking, gating, and reset strategies
• Contribute to design reviews, documentation, and technical mentoring across HBM programs #

Required Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant industry experience, or a Master's degree with 4+ years of relevant industry experience.
• 2 + years of experience in high‑speed digital datapath design (memory, SerDes, or SoC datapath).
• 2+ years of hands‑on experience with digital schematic build, RTL, or mixed‑signal datapath implementations.

#

Preferred Qualifications:

• Strong understanding of

HBM/DRAM

architectures, including read/write data flow, timing, and multi‑channel operation.

• Working knowledge of layout and floorplanning considerations for high‑speed datapath.
• Experience with static timing analysis (STA) and timing‑closure methodologies.
• Familiarity with advanced process‑node challenges related to signal integrity, skew control, and power optimization.

Job Profile(s): Systems Design Engineer 4

Relocation Level:

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