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Now viewing: Senior Mixed-Signal IC Design Engineer DLL, Delay Line & Clocking Architectures
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Insight Global
Senior Mixed-Signal IC Design Engineer DLL, Delay Line & Clocking Architectures
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Job Description
Job Description Design and develop Delay Locked Loops (DLLs) for high-performance clock generation, synchronization, and phase alignment.
Architect and optimize programmable delay lines and delay blocks for precise timing control.
Develop clock distribution solutions including:
Clock treesClock buffersClock dividersClock deskew circuitsDuty-cycle correction circuitsDesign and analyze DLL phase detectors, phase interpolators, charge pumps, and loop control circuitry.
Perform extensive jitter analysis, including:
Random jitterDeterministic jitterSupply-induced jitterClock uncertaintyPhase noise contributionsOptimize clocking architectures for low skew, low power, and high timing accuracy.
Analyze delay-line performance across PVT corners and process variations.
Develop timing closure strategies with digital implementation and physical design teams.
Support clock architecture development for high-speed mixed-signal and data converter systems.
Collaborate with layout engineers to minimize clock path mismatch and parasitic effects.
Validate silicon performance through lab characterization and clock integrity measurements. Skills and Requirements BS, MS, or PhD in Electrical Engineering.5+ years of experience in analog or mixed-signal IC design.
Strong experience designing:
DLLs (Delay Locked Loops)Delay linesPhase alignment circuitsClock conditioning circuitsDeep understanding of clock generation and distribution architectures.
Experience with:
Clock tree designClock deskew techniquesPhase detection circuitsTiming recovery systemsStrong knowledge of:
Jitter analysisPhase noiseTiming uncertaintySkew optimizationLoop stabilityExperience with transistor-level design in advanced CMOS technologies.
Proficiency with Cadence Virtuoso and industry-standard simulation tools. We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to HR@insightglobal.com.
Architect and optimize programmable delay lines and delay blocks for precise timing control.
Develop clock distribution solutions including:
Clock treesClock buffersClock dividersClock deskew circuitsDuty-cycle correction circuitsDesign and analyze DLL phase detectors, phase interpolators, charge pumps, and loop control circuitry.
Perform extensive jitter analysis, including:
Random jitterDeterministic jitterSupply-induced jitterClock uncertaintyPhase noise contributionsOptimize clocking architectures for low skew, low power, and high timing accuracy.
Analyze delay-line performance across PVT corners and process variations.
Develop timing closure strategies with digital implementation and physical design teams.
Support clock architecture development for high-speed mixed-signal and data converter systems.
Collaborate with layout engineers to minimize clock path mismatch and parasitic effects.
Validate silicon performance through lab characterization and clock integrity measurements. Skills and Requirements BS, MS, or PhD in Electrical Engineering.5+ years of experience in analog or mixed-signal IC design.
Strong experience designing:
DLLs (Delay Locked Loops)Delay linesPhase alignment circuitsClock conditioning circuitsDeep understanding of clock generation and distribution architectures.
Experience with:
Clock tree designClock deskew techniquesPhase detection circuitsTiming recovery systemsStrong knowledge of:
Jitter analysisPhase noiseTiming uncertaintySkew optimizationLoop stabilityExperience with transistor-level design in advanced CMOS technologies.
Proficiency with Cadence Virtuoso and industry-standard simulation tools. We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to HR@insightglobal.com.
Benefits
- Dental Insurance