ASIC Design Engineer

• Neural Engine DMA Apple
• 4.1 Sunnyvale, CA Job Details $129,300
• $194,700 a year 4 hours ago Benefits Employee stock purchase plan Health insurance Dental insurance RSU Retirement plan Qualifications Bachelor's degree Full Job Description Computational photography, live language translation, and countless other on-device AI capabilities depend on moving enormous amounts of data between memory and compute at exactly the right time.

As part of our Silicon Engineering Group, you will help build the high-performance DMA engines responsible for moving model weights and activation tensors between the memory subsystem and the Apple Neural Engine. In this role, you will collaborate closely with architecture and verification teams across the full front-end design cycle. The work you contribute ships in Apple products used by billions of people every day. Description As an ASIC Design Engineer on the ANE DMA Design team, you will contribute to the design of DMA subsystem blocks from microarchitecture specification through tapeout. High-performance DMA involves hard problems in data movement, throughput, and correctness. In this front-end design role, your work will include: Writing well-parameterized RTL structured for correct synthesis, clean timing, and low power, along with assertions and cover points that encode design intent and ensure verification completeness.

Executing front-end implementation tasks:

synthesis, timing closure, area and power analysis, linting, and logic equivalence checks. Collaborating with fellow designers and architecture teams to understand design requirements, contribute to micro-architectural specifications, and develop solutions that meet performance, power, and area targets. Working closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and ensuring the design's intended behavior is fully exercised. Preferred Qualifications Familiarity with Verilog or SystemVerilog and core digital design fundamentals: finite state machines, pipelining, parallelism, and timing. Some exposure to on-chip bus protocols such as AMBA (AXI, AHB, APB). Interest in or exposure to system-level concepts: how data moves through a SoC, flow control between producers and consumers, memory system latency and bandwidth trade-offs, and how hardware and software divide responsibilities at system boundaries. Background in or curiosity about high-bandwidth domains: networking, image and video processing, multimedia, or AI/ML. Familiarity with scripting languages (Python, Perl, Tcl) for design automation. Clear technical writing skills and the habits of asking good questions, flagging issues early, and contributing constructively in design reviews. Minimum Qualifications Bachelors Degree plus 0 years of industry experience Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses

• including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about

Apple Benefits Note:

Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.