ASIC STA & SYNTHESIS ENGINEER

ASIC STA & SYNTHESIS ENGINEER

Vhunt4u Austin, TX Job Details 17 hours ago Qualifications Engineering Analysis skills Bachelor's degree in engineering Master's degree in electrical engineering Senior level Electrical Engineering Master's degree in engineering Digital design

Full Job Description Work Location :

Austin, Bangalore, Cambridge, Malaysia, San Jose Work Expertise :

5 Years - 15

Years Desired Profile :

Bachelor's / Master's degree in engineering from

EEE / E&C

with expertise in

ASIC STA / SYNTHESIS

Timing analysis and logic synthesis of digital designs. The role focuses on achieving timing closure and optimizing design performance, power, and area. Perform RTL synthesis using industry-standard tools Should be capable to analyze and run LEC to ensure gate level netlist matches the original RTL Run Static Timing Analysis (STA) and identify timing violations Fix setup and hold violations across different corners/modes Work on constraints development (SDC creation and validation) Analyze timing reports and improve design quality Collaborate with RTL, DFT, and Physical Design teams Support timing closure during implementation and signoff Strong understanding of digital design fundamentals Knowledge of synthesis and STA flow Familiarity with timing concepts (setup, hold, skew, latency) Experience with EDA tools (Experience with EDA tools - (Genus, Tempus)

VISA SPONSORED FOR

MALAYSIA