View More Jobs Director, ASIC Physical Design United States (Hybrid) We are seeking an experienced and visionary Director of ASIC Physical Design to strategically lead and direct our global physical design engineering teams. This pivotal role involves driving the physical implementation of complex ASICs from RTL to GDSII, with a strong emphasis on achieving optimal performance, ultra-low power , and area (PPA) targets on the latest technology nodes . The successful candidate will be responsible for defining advanced physical design methodologies, managing and developing teams across the USA, India, and Italy , fostering innovation, and collaborating closely with cross-functional engineering groups to deliver high-quality, manufacturable silicon, ensuring first-pass success under aggressive schedules . Your responsibilities

Strategic Leadership & Global Team Management:

Define and execute the physical design roadmap, strategy, and technical direction for multiple ASIC projects, aligning with overall product and technology goals. Lead, inspire, and strategically manage a distributed team of physical design engineers across the USA, India, and Italy.

Team Development & Training:

Mentor, grow, and build a high-performing global team, fostering a culture of technical excellence, collaboration, and continuous improvement. Specifically, drive the training and adoption of advanced methodologies, including the introduction and implementation of Customer Owned Tooling flow to ensure efficient and robust GDSII release.

Advanced Methodology & Flow Development:

Drive the development, adoption, and continuous improvement of cutting-edge physical design methodologies, flows, and best practices, particularly for advanced and latest technology nodes with a strong focus on low-power design techniques.

Project Execution & PPA Optimization:

Oversee the complete physical design cycle, including floor-plan, power grid design, placement, clock tree synthesis (CTS), routing, timing closure (STA), power integrity (IR/EM), physical verification (DRC/LVS), and DFM/DFY. Ensure all physical design activities are optimized to achieve aggressive PPA targets (performance, ultra-low power , area) for complex digital and mixed-signal ASICs on leading-edge process technologies. Cross-Functional Collaboration for

First-Pass Silicon:

Partner effectively and interact heavily with architecture, RTL design, DFT, CAD, package, and test teams to ensure seamless integration and successful first-pass silicon under tight development schedules. Proactively identify and resolve inter-team dependencies and technical challenges.

Vendor & IP Management:

Manage relationships with EDA tool vendors and IP providers, evaluating new technologies and ensuring effective tool deployment and support.

Risk Management:

Identify potential technical risks and develop mitigation strategies throughout the physical design process.

Budget & Resource Planning:

Manage departmental budgets, resources, and project schedules to ensure efficient execution and delivery across global sites. Your skills and experience Master's degree in Electrical Engineering, Computer Engineering, or a related field; Ph.D. preferred. 15+ years of progressive experience in ASIC physical design, with at least 8 years in a leadership or management role overseeing large, multi-site teams. Deep expertise in all aspects of the ASIC physical design flow, including floorplanning, power planning, placement, CTS, routing, timing closure, power analysis, and physical verification. Proven track record of successfully leading multiple complex ASIC tape-outs on advanced and latest technology nodes (e.g., 7nm, 5nm, 3nm and beyond), with significant experience in implementing and optimizing low-power design techniques. Demonstrated experience in introducing and deploying new physical design methodologies, including experience with CoT flow, leading to successful GDSII release. Strong command of industry-standard EDA tools from vendors such as Synopsys, Cadence, and Siemens EDA. Understanding of AI for Physical Design flow development & required automation. Understanding of Chip level IR analysis with required Package models. Exceptional leadership, communication, and interpersonal skills, with the ability to influence and drive results across diverse, geographically dispersed teams. Demonstrated ability to attract, develop, and retain top engineering talent globally.

Preferred Qualifications:

Experience with custom layout and mixed-signal integration. Familiarity with various memory compilers, SerDes, and other hard IP integration. Experience with design for testability (DFT) and design for manufacturing (DFM) considerations. Understanding of package and board-level interactions with silicon. At Nokia, we want every candidate to be able to perform their best. If you need any adjustments or support during the recruitment process, please let us know. All requests are treated confidentially. Apply Now Job Info Job Category Applied R D Posting Date 09/29/2026 Degree Level Bachelor's degree Job Schedule Full time Job Type Experienced Job Identification 40941 Will

NSA/CAPS

approval be required? (E.g., accessing a US Customer Network?) No Role Type People Manager Laptop - support with ordering needed Yes Salary Range $179,000 to $256,000 Experience level Experienced Locations 6373 San Ignacio Avenue, San Jose, California, 95119-1200, US (Hybrid) Regular or Temporary Regular Legend Jobs at a location Group of locations © Oracle Corporation Terms Legal Notices Use control and scroll to zoom the map Use two fingers to move the map

Similar Jobs See More Jobs AI Statement:

Nokia embraces the strategic use of Artificial Intelligence (AI) within our recruiting process to enhance the candidate experience and significantly improve our operational efficiencies. By leveraging AI-powered tools, we aim to create a more responsive and equitable journey for all applicants. Concurrently, we advocate for the intelligent, ethical, and safe use of AI by candidates and applicants when preparing and submitting their applications for our roles. This includes ensuring that any AI-generated content is thoroughly reviewed for accuracy, originality, and relevance, and that its use aligns with principles of transparency and integrity. Our goal is to foster a recruitment environment that benefits from technological advancements while upholding fairness, authenticity, and human oversight.