Senior FPGA Design Engineer Three Point Solutions, Inc. - 4.4 Rochester, NY Job Details Full-time $110,000 - $140,000 a year 8 days ago Benefits Relocation assistance Dental insurance 401(k) Paid time off Parental leave Qualifications Digital signal processing Embedded systems
FPGA VHDL
Verilog Telecommunications systems Linux FPGA circuit design
Vivado Full Job Description Job Title:
Senior FPGA Design & Verification Engineer -
VHDL/SystemVerilog Location:
Rochester, NY Job Type:
Full-Time Permanent Industry:
Aerospace / Defense Overview Seeking an experienced FPGA Engineer for tactical and radio communication systems. The role involves FPGA design, verification, DSP/modem implementation, and embedded communication system development. Key Responsibilities
- Design, develop, and verify FPGA firmware using VHDL/Verilog
- Implement DSP, modem, waveform, and signal-processing solutions
- Create SystemVerilog test benches, verification plans, and perform validation/testing
- Integrate FPGA firmware with hardware platforms and support troubleshooting
- Work with cross-functional teams on system architecture, reviews, and technical documentation Required Skills
- Strong
FPGA/ASIC
development and verification experience
- Hands-on experience with VHDL, Verilog, and SystemVerilog
- Experience with Vivado, Quartus, Libero, and Linux environments
- Background in DSP, modem implementation, and embedded communication systems
- Ability to obtain US Secret Security Clearance Preferred Skills
- MATLAB/Simulink, TCL or Python scripting
- UVM, Mentor Questa/Visualizer
RF/MODEM
testing experience
- Experience with GIT, SVN, or Bitbucket Qualifications
- Bachelor's + 7 years, Graduate Degree + 9 years, or 13+ years relevant experience Benefits
- Full benefits, relocation assistance, PTO, holidays, 401(k), insurance, parental leave, and education assistance Additional Info
- 9/80 Schedule (every other Friday off)
- No travel required
- Visa sponsorship not available
- Clearance sponsorship available IND_
ENG Pay:
$110,000.00 - $140,000.00 per year
Benefits:
401(k) Dental insurance Paid time off Parental leave
Experience:
FPGA development using
VHDL/Verilog :
7 years (Required) DSP & communication systems : 4 years (Required) FPGA verification : 5 years (Required)
Work Location:
In person