ASIC Design Engineer Epia Neuro Alameda, CA Job Details Full-time $100,000 - $140,000 a year 6 hours ago Benefits Paid parental leave Health insurance Parental leave Qualifications Project reporting Circuit testing Signal processing circuit design Electrical engineering training Design engineering Linux Project stakeholder communication Debugging Full Job Description About Us Epia Neuro is a neural technology company developing intent-driven systems designed to restore function and independence for people living with neurological conditions. Its platform integrates implantable neural interfaces, adaptive algorithms, and assistive devices to translate neural intent into real-world action. The company's initial focus is stroke-related motor impairment, with expansion in cognitive decline and other neurological disorders, focusing on long-term solutions for the growing aging population. The Role We're looking for an ASIC Design Engineer who wants to be involved in all aspects of design cycle: documentation, design, pre-silicon verification, and post-silicon validation. The team is small in a startup environment, so the role is dynamic and all efforts will have visible impact. You'll work alongside senior engineers across all disciplines of ASIC design and have ownership from day one. Ideal candidate is inquisitive and a creative problem solver, who likes to tinker with whatever resources available. Location This role is expected to work on site from our Alameda Headquarters 5 days a week. How We Work We are intentional. We prioritize and are thoughtful about how we use others' time. We care for others. We prioritize safety both for patients and one another. We own outcomes, not just tasks. Our work demands the highest standards because it impacts real patients and real lives. Humility is a strength. We are honest about what we know and what we don't know. Getting it right matters more than being right. What You'll Do Document and implement module designs Simulate module functions and support pre-silicon verification Build/develop test HW/SW to validate chips Validate and characterize chips across configurations Document test plans and test reports Root-cause issues beyond surface-level symptoms Qualifications Bachelor's degree in Electrical Engineering/Computer Science, plus relevant industry experience in ASIC design — or a Master's/PhD with hands-on ASIC design experience through university lab or project work Strong written and verbal communication skills — you'll need to document your work clearly and communicate project status, good or bad Comfortable working independently in a Linux/Linux-like environment, working with open-source projects Experience with: Analog circuit design Digital (RTL) design Programming Testing/debugging designs or systems Preferred experiences High-precision, low-noise, low-power circuit design (e.g., bandgap reference, high-speed

IO, PLL, ADC

) Design/work with industry-standard interfaces, such as SPI and I2C Test automation Experience with the Cadence tool suite Design or research related to medical devices (e.g., neuroscience, biomedical instrumentation) A track record of tinkering — work-related and/or personal projects (e.g., Raspberry Pi builds) to solve everyday problems Managing design tools or vendor-supplied libraries (e.g., PDKs) in the university lab or industry setting Benefits Full-time employees are eligible for the following benefits listed below. Competitive base salary with equity 100% of healthcare coverage for you and your dependents Generous vacation policy Paid parental leave Work from our beautiful waterfront office in Alameda, CA, with access to collaborative spaces and labs.

Compensation Range:

$100K - $140K