Design Engineer III
Job
Epitec
Sunnyvale, CA (In Person)
Full-Time
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Job Description
Design Engineer III Epitec
GDSII flows at 7nm and below , with strong collaboration across RTL and physical design teams. Key Responsibilities Perform comprehensive power analysis across all design stages, from RTL through GDSII Develop, improve, and automate power analysis and modeling flows Analyze large datasets for power estimation and modeling , leveraging scripted and ML?based approaches Identify power inefficiencies and provide actionable RTL optimization feedback Support low?power implementation and sign?off , including: Power gating Multi?voltage designs UPF?based methodologies Minimum Qualifications (Must?
Have) Hands?on experience with RTL?to?
GDSII design flows at 7nm or below Strong expertise in low?power design and signoff Power gating Multi?voltage rails Unified Power Format (UPF) Proven experience using PrimeTime PX / PrimePower for power analysis and reduction Proficiency in Python scripting Experience leveraging ML / AI frameworks for analysis or modeling Solid working knowledge of RTL design principles Experience with RTL power optimization tools (e.g., Power?
Artist) Ability to rapidly learn, iterate, and improve power solutions Preferred Qualifications Experience with synthesis and Place & Route (PnR) flows Power analysis of IP blocks and development of runtime estimation models Data analysis, modeling, and machine learning-driven power estimation Familiarity supporting software or firmware teams with power modeling inputs
- 3.4 Sunnyvale, CA Job Details Contract 1 day ago Benefits Paid time off Qualifications Machine learning/AI-based analysis Bachelor's degree AI Semiconductor experience Machine learning frameworks Python Full Job Description Power Analysis Engineer
Advanced Chip Design Location:
ONSITE- US Austin, TX (Primary), Sunnyvale, CA (2nd option)
Employment Type:
W2 Contract- Long?
GDSII flows at 7nm and below , with strong collaboration across RTL and physical design teams. Key Responsibilities Perform comprehensive power analysis across all design stages, from RTL through GDSII Develop, improve, and automate power analysis and modeling flows Analyze large datasets for power estimation and modeling , leveraging scripted and ML?based approaches Identify power inefficiencies and provide actionable RTL optimization feedback Support low?power implementation and sign?off , including: Power gating Multi?voltage designs UPF?based methodologies Minimum Qualifications (Must?
Have) Hands?on experience with RTL?to?
GDSII design flows at 7nm or below Strong expertise in low?power design and signoff Power gating Multi?voltage rails Unified Power Format (UPF) Proven experience using PrimeTime PX / PrimePower for power analysis and reduction Proficiency in Python scripting Experience leveraging ML / AI frameworks for analysis or modeling Solid working knowledge of RTL design principles Experience with RTL power optimization tools (e.g., Power?
Artist) Ability to rapidly learn, iterate, and improve power solutions Preferred Qualifications Experience with synthesis and Place & Route (PnR) flows Power analysis of IP blocks and development of runtime estimation models Data analysis, modeling, and machine learning-driven power estimation Familiarity supporting software or firmware teams with power modeling inputs
Education Required:
Bachelor's degree inElectrical Engineering, Computer Engineering, or Computer Science Preferred:
Master's degree (not required) #PowerAnalysis #LowPowerDesign #VLSI #SemiconductorJobs #RTLDesign #ChipDesign #PythonEngineering #EDA #LI-KT1 #INDOEMSimilar remote jobs
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