RTL Design Engineer, TPU Compute Google - 4.3 Sunnyvale, CA Job Details Full-time $138,000 - $197,000 a year 4 hours ago Qualifications Verilog Digital circuit design

Full Job Description Note:

By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Austin, TX, USA .

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital design experience using SystemVerilog RTL. Experience with Computer Architecture.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience interacting with software, architecture, and other cross-functional teams. Experience applying computer architecture principles to solve open-ended problems. Knowledge of processor design, accelerators, or memory hierarchies. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US:

$138000 - $197000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google. Responsibilities Work on their own to create and review Compute subsystem's design microarchitecture specifications. Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines. Work with design validation (DV) teams to create testplans to verify, and debug design RTL. Work with physical design teams to ensure design meets physical requirements and timing closure. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.