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QU
QORVO US, INC.
Staff Layout Design Engineer (10499)
Career Insights for Manufacturing Process Engineer
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Based on Florida data
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What they do
A Manufacturing Process Engineer develops workflow, work station, and equipment improvement recommendations within a company's manufacturing environment. Fine tunes manufacturing processes by researching, designing, modifying, and testing manufacturing methods and equipment. Evaluates manufacturing processes, applies knowledge of product design, fabrication, assembly, tooling, and material.
$90,648 / year median in Florida
-1% projected decline
Job Description
Job Description Help for Job Description. Opens a new window. Veterans Preference In this position, you will work closely with design engineering groups to complete the layout and verification of high-performance Switches, Power Management Devices, and Integrated Products using Cadence Virtuoso XL and Mentors Calibre tools.
Responsibilities:
Work closely with design engineers to ensure proper circuit performance Design analog and RF layout Understand device matching techniques Teamwork skills, including written and verbal communications, with both local and remote design teams Layout planning and integration skills from small block to full chipSkills and Qualifications:
Associate's degree in electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience Ability to layout analog circuitry in a size/time constrained environment Understand layout techniques such as common centroid, matching, isolation, and the use of dummy devices Ability to solve design problems using technical skills, intuition, and creativity Proficiency in floor planning and assembly from block to full chip level Knowledge of Cadence and Mentor Verification tools LVS troubleshooting and debug skills Ability to work individually and in a team-orientated environment Employer conductsBackground Checks Preferred Skills and Qualifications:
BSEE/BS Engineering Technology or related program Comfortable with CMOS and SOI technologies across multiple foundry PDKs Ability to contribute ideas for improved schematic and layout interaction Schematic entry for dummy devices, resizing devices, and debugging LVS issues. This position is not eligible for visa sponsorship by the Company. We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.Benefits
- Dental Insurance