Design Engineer

Avanciers are looking for a skilled Physical Design Engineer with hands-on experience in backend VLSI design for ASICs/SoCs. The role involves block-level and top-level physical design implementation including floorplanning, placement, CTS, routing, timing closure, and signoff activities. Key Responsibilities Floorplanning, placement, CTS, routing, and timing closure Power planning, IR drop, and signal integrity analysis Chip-level integration and physical verification Support netlist-to-GDSII implementation flow Work closely with DFT and front-end teams Develop automation scripts using Tcl/Perl/Python/Shell Required Skills 5-18 years of ASIC/SoC Physical Design experience Strong knowledge of STA, CTS, routing, and signoff flows Hands-on experience with Innovus, ICC2, PrimeTime, Calibre Strong scripting and debugging skills Experience with advanced technology nodes preferred

Note:

Only candidates with 5-18 years of experience will be considered.