$274,800.

00 / yr United States, Washington, Redmond Aug 04, 2026\nOverview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's \"Intelligent Cloud\" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Subsystem Engineer (Design or DV) to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Subsystem Engineer (Design or DV) with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Subsystem Engineer (Design or DV) to join the team. Responsibilities TheAISoCsiliconteam isseekinga Principal Subsystem Engineer (Design or DV) to deliver premium-quality designs once considered impossible. Weare responsible fordeliveringcutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.

Team is currently looking for subsystem design and DV leads. Technically lead one or more Subsystems as a design or DV engineer.\nCollaborate across teams on vertical and horizontal reuse of components.\nProvide technical leadership through mentorship and teamwork.\nWork effectively with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up.\nDeep understanding of many of the following: complex subsystems (such as PCIE, HBM, imaging or control), fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement.\nExperience in design or DV domains.\nDesign includes but not limited to

Bandwidth, latency, utilization, and power tradeoffs while driving synthesis, timing constraints, floor-planning awareness, and performance tuning (Design). Verilog/System Verilog, microarchitecture specification development, RTL coding, integration, and design quality closure (CDC, lint, RDC) (Design).\nOR\nDV expertise includes but not limited to
Deep expertise in Design Verification (DV), including development of verification strategies and test plans, creation and debugging of UVM-based constrained-random testbenches, scoreboards, checkers, and assertions, implementation of functional coverage and coverage closure, and application of Agile methodologies for code reviews, sprint execution, and feature deployment.

Qualifications Required Qualifications:

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

Microsoft Cloud Background Check:

This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.\nThis role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.

As a condition of employment, the successful candidate will be requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status(e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.

To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

9+ years of related technical engineering experience\nOR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience\nOR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience\nOR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.\nExperience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments.\nExperience with design quality and static checks, DFT implementation and hand off to physical design.\nExperience in design or DV domains.\n8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.\n8+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug\nOR\n9+ years of experience in either design and integration or DV with a proven track record of delivering high-performance IP, SS or SOC testbenches.\nExperience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM).\n12+ years of relevant experience.\n5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams.\nLead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar.\nExperience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs.\nExperience in Scripting language such as Python or Perl.\nHands on experience in Formal property verification(DV) #SCHIE Silicon Engineering IC5

The typical base pay range for this role across the U.S. is USD $142,800
$274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and York City metropolitan area, and the base pay range for this role in those locations is USD $188,000
$304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:\nhttps://careers.microsoft.com/us/en/us-corporate-pay This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. 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Principal Subsystem Engineer (Design or DV)