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Bolt Hiring

Physical Design Engineer

Pay: $80–$85/hr
Posted: 2 days ago
Location: Palo Alto, CA (Onsite)
Last Updated: 21 hours ago
Hours: Full-Time
Expires: 10/30/2026
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Job Description

Experience:
Exposure to
TSMC 2NP/3NP
is must Perform end‑to‑end physical design flow: Floorplanning Power planning (PG grid, IR) Placement & optimization CTS (Clock Tree Synthesis) Routing Post‑route optimization Achieve timing closure across all modes and corners Resolve DRC, LVS, ERC and signoff violations Handle low‑power design techniques: Multi‑Vt, Multi‑voltage (UPF) Power gating, clock gating Perform physical verification and signoff: STA (Primetime) SI / Crosstalk IR drop & EM analysis Work on advanced nodes (7nm, 5nm, 3nm or below) Collaborate with: RTL & Micro‑architecture teams DFT & Test engineers Foundry and CAD teams Debug complex timing, congestion, power, and variability issues Drive methodology improvements and automation (scripts/flows)
Pay:
$80.00 - $85.00 per hour Expected hours: 40.0 per week
Work Location:
In person