Senior Physical Design Signoff Engineer

Job Title:

Senior Physical Design Signoff Engineer (Top-Level SoC)

Location:

SanJose CA Contract Experience:

8+ Years Job Summary We are hiring experienced Physical Design Signoff Engineers for advanced-node SoC projects (7nm/5nm/3nm). Candidates should have strong expertise in full-chip signoff with multiple successful tapeouts and the ability to drive signoff-to-tapeout closure independently. Key Responsibilities Lead top-level signoff activities for high-performance SoCs. Collaborate with RTL, PD, STA, Power Integrity, Clocking, and Foundry teams. Drive timing, power integrity, clock, and reliability closure. Debug and resolve full-chip implementation/signoff issues. Improve signoff methodologies for better TAT and PPA. Required Expertise (Any One Area) EMIR / Power Integrity IR Drop, EM analysis, PDN optimization

Tools:

RedHawk-SC, Voltus Timing / STA MMMC timing closure, ECOs, full-chip

STA Tools:

PrimeTime/PT-SI, Tempus Clock Distribution CTS, H-Tree/Mesh clock architecture, skew optimization

Tools:

Innovus, ICC2 Required Skills 8+ years in Physical Design/Signoff Experience with 2-3 tapeouts on 7nm/5nm/3nm Strong knowledge of OCV, AOCV/POCV, statistical timing

Scripting:

Tcl, Python, Perl Excellent debugging and communication skills Preferred Experience with HPC, AI accelerators, large-scale SoCs Familiarity with TSMC/Samsung/Intel signoff flows 2.5D/3D IC packaging experience is a plus