175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client locations throughout the U.S.
Position Responsibilities:
Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced process nodes (3nm or below). Take care of floor-planning, CTS (Clock Tree Synthesis), Route use ICC2, Innovus tools related to Cadence and Synopsys. Optimize design with multi-corner multi-mode (MCMM) timing constraint. Fix setup, hold, transition, capacitance, crosstalk violation, min pulse width (MPW), signal EM (Electromigration) and solving congestion, short, skew, etc. Work on high-speed and complicated clock structure designs with a large number of memories and instances. Use PrimeTime to check and debug timing. Analyze floorplan to reduce congestion using advanced scripting techniques generate a robust clock tree by analyzing the sync points and achieving low latency and minimal power. Work on Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, Power. Control timing budgets between blocks & the top-level chip using timing models such as
ETM, ILM.
Build ECO environments for place and route tools to fix all timing violations. Work on Power Analysis and IR Drop Analysis to meet the requirements. Work on Physical Verification (PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS), Antenna, Electrical Rule Check (ERC), Design for Manufacturing (DFM). Work on logic equivalence check (LEC) for Pre- Post Place and Route design.
Position Requirements:
Bachelor's degree (or foreign equivalent) in Electronics Engineering, or a related field, PLUS five (5) years of experience in the job offered or a related position. Experience must include demonstrable knowledge of: The full Place & Route design flow incl. logical synthesis, STA, DFT, Placement, Clock Tree Synthesis & physical verification; hardening highspeed, low power CPU designs; design of large SOC full chip & block level P&R using advance Process technologies: advanced process nodes (3nm or below); high-speed interfaces at chip level; clock tree creation incl. sync points & achieving low latency & minimal power; design w/ multicorner multi-mode timing constraints; STA; control of timing budget between blocks & chip using timing model such as
ETM, ILM
; ECO environments for place & route tools to fix timing violations. Travel to unanticipated client locations throughout the U.S., approximately 30%, as required. May telecommute from any location within the U.S. Apply at careers.quest-global.com and reference Job Code 28290.0330
Pay Range:
$130,333 - $160,000 Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.
