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V
VanderHouwen
Principal Design Engineer
Career Insights for Automotive Engineer
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Based on Oregon data
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What they do
An Automotive Engineer creates and improves mechanisms for automotive components.
$115,450 / year median in Oregon
+3% projected growth
Job Description
Principal Design Engineer Our client is seeking a Principal Design Engineer to play a key role in the design and development of advanced semiconductor IP solutions used in cutting-edge display, imaging, and high-performance computing applications. This is an opportunity to join a collaborative, engineering-driven team where innovation, technical ownership, and code quality are highly valued. The ideal candidate is a hands-on design expert who enjoys solving complex technical challenges, mentoring others, and delivering robust solutions in a fast-paced, growth-oriented environment. This role is fully remote with occasional office visits in Portland, Oregon. Applicants located in Portland, Oregon or Seattle, Washington are preferred. Principal Design Engineer Responsibilities Lead the architecture, design, and development of advanced RTL-based IP solutions for complex ASIC and SoC applications. Design and implement high-quality RTL using Verilog and/or SystemVerilog with a strong emphasis on maintainability, performance, and reliability. Develop innovative micro-architectures to address challenging video, display, and high-speed data processing requirements. Collaborate with customers and cross-functional engineering teams to support successful IP integration and technical problem resolution. Perform and support block-level and system-level verification activities using industry-standard verification methodologies and tools. Drive design quality through simulation, code reviews, linting, clock domain crossing (CDC) analysis, and formal verification techniques. Mentor engineers by providing technical guidance, promoting engineering best practices, and fostering a culture of technical excellence. Partner with internal teams to improve engineering workflows while leveraging AI-assisted tools for automation and validation where appropriate. Principal Design Engineer Qualifications 8+ years of experience designing RTL for ASIC, SoC, or complex digital IP development. Strong expertise with Verilog and/or SystemVerilog for complex digital design. Hands-on experience with DisplayPort, Display Stream Compression (DSC), or comparable display interface technologies. Proven success delivering high-quality digital designs from architecture through implementation. Experience with block-level and system-level verification, including verification IP or bus functional models. Proficiency with industry-standard simulation tools such as Cadence, Synopsys, or Mentor Graphics. Experience with successful ASIC tape-outs, linting tools, CDC analysis, and formal verification is preferred. Strong understanding of video or image processing systems, high-speed SerDes interfaces, and video or image compression technologies is highly desirable. Demonstrated success working in smaller, collaborative engineering environments where initiative, ownership, and adaptability are essential. Excellent communication, problem-solving, and technical leadership skills with the ability to work independently while mentoring others.