Sr Physical Design Engineer (Synopsys Fusion / GF 12LP)

• Remote
• Full Time / Contract Encore Semi, Inc.
• 3.7 San Jose, CA Job Details Full-time | Contract $150,000
• $165,000 a year 11 hours ago Benefits AD&D insurance Paid holidays Disability insurance Health insurance Dental insurance 401(k) Flexible spending account Tuition reimbursement Paid time off Employee assistance program Vision insurance Life insurance Qualifications Semiconductor electronics Bash Perl Design engineering Python Full Job Description Sr Physical Design Engineer (Synopsys Fusion / GF 12LP)•Remote•Full Time /

Contract Full-time:

Salary

+ Benefits

+ Bonuses /

Contractor Work Status:

US Citizen or Lawful Permanent Resident. We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out.

Core Technical Environment & Ongoing Responsibilities:

Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA).

Implementation:

Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler).

Timing & Signoff:

Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC.

FinFET Optimization:

Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management.

Verification:

Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV).

Automation:

Maintain robust Tcl, Python, or Perl scripts to automate workflows.

Qualifications:

10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm). Deep expertise in rapid

DRC/LVS/ERC

closure and final tape-out procedures. Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime. Strong scripting skills (Tcl, Python, Bash).

Preferred:

Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre. The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.

Full-Time Benefits:

15 days of PTO per calendar year 10 paid Holidays per calendar year

Comprehensive Medical Benefits:

Company covers 80% of premiums for

Employee and Dependents Dental & Vision:

Company covers 50% of premiums for

Employee and Dependents Voluntary Benefits:

Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance Employee Assistant Program (EAP) 401k

• Traditional & Roth Life/AD&D and Long-Term Disability Tuition reimbursement Equal Opportunity Policy Statement Encore Semi, Inc.

is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances. Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

LinkedIn :

: https://www.linkedin.com/in/rtl2gds/