Principal Verification Engineer

Principal Verification Engineer at Fidelis Companies Principal Verification Engineer at Fidelis Companies in El Verano, California Posted in about 2 hours ago.

Type:

full-time

Job Description:

Principal Verification Engineer Full Time Opportunity Fully onsite in San Francisco Bay Area $450K+ Total Compensation- Bonus, Base, and RSU's (Depends on skillset and experience level) Industry leader and well?established semiconductor design organization building next?generation ASICs and custom AI accelerators . This team is responsible for delivering high?performance IP used across advanced compute and connectivity products. This role focuses on IP? and subsystem?level verification , including complex blocks such as SerDes and processor?based subsystems, within large SoC environments. What You'll Do Own verification of IP blocks and subsystems used in advanced ASIC and custom AI chip designs Architect and implement modern verification environments and reusable test benches Define and execute block? and subsystem?level verification strategies and test plans Drive verification closure using functional coverage, assertions, formal methods, and debug Collaborate closely with design, architecture, physical design, and validation teams Participate in bring?up and debug of complex IP , including high?speed and processor?based subsystems Required Background BS/MS in Electrical Engineering, Computer Engineering, or equivalent experience 10+ years of hands?on SoC / ASIC verification experience Proven experience architecting scalable verification environments Deep knowledge of industry?standard verification methodologies and tools Strong expertise in: SystemVerilog & UVM RTL design and verification Block? and subsystem?level verification planning Hands?

on experience with:

CDC checks Formal verification Functional coverage Gate?level debug Emulation / acceleration tools Strong debugging and problem?solving skills, with a track record of delivering under tight schedules Nice to Have Familiarity with SerDes architectures, protocols, and bring?up Knowledge of processor microarchitectures and bus protocols Experience building and maintaining automated verification frameworks Background working on large, complex SoCs with multiple IP integrations