JB061568 - Lead ASIC DFT Engineer

USM Jobs / Lead

ASIC DFT

Engineer High Contract

JB061568

- Lead

ASIC DFT

Engineer Apply Start Date:

Interview Types Skills ASIC DFT, Visa Types Green Card, US Citiz.. Job Description Apply for this Job Required Skills & Qualifications Strong hands-on experience in

ASIC DFT

with end-to-end ownership. Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis. Experience with MBIST implementation and verification; SMS experience preferred. Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred. Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation. Proven post-silicon debug and silicon bring-up experience. Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges. Strong communication skills and the ability to work independently with minimal ramp-up. Preferred Experience MBIST post-silicon validation. ATPG simulations and fault coverage debug.

DFT RTL, DFD, DFT

verification, and IP-level DFT integration. DFT SDC creation and DFT timing closure support. Boundary scan, iJTAG, SSN, and design-for-debug methodologies.

TCL/PERL

scripting for DFT automation, reporting, and debug. Experience working across multiple ASIC technology nodes and complex product development cycles. Familiarity with yield learning, diagnosis, and manufacturing test optimization. Name

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Country United States Submit Information Locations San Jose, CA Position Open to Anywhere in the US, but will work on-site Industry Manufacturing Status Open Job Age 1 Day's Created Date 05/07/2026 No.of Positions 1 Duration 12 Zip Code