DFT Engineer Talent on staffing Santa Clara, CA Job Details Full-time | Contract $90,600 - $110,000 a year 21 hours ago Qualifications Teamwork Engineering development testing Tooling Analysis skills SoC Simulation tools Analytical thinking Python Debugging Cross-functional communication Full Job Description Job Summary We are looking for experienced DFT Engineers with strong hands-on experience in DFT and ATPG for ASIC/SoC designs . The ideal candidate will have expertise in scan-based testing, ATPG, MBIST, clock DFT, and industry-standard

DFT/ATPG

tools. Key Responsibilities Develop and implement DFT solutions for complex ASIC/SoC designs Perform scan insertion, scan architecture development, and scan validation Generate, analyze, debug, and optimize ATPG patterns Work on MBIST architectures, memory testing, and diagnostics Support IO test methodologies, interfaces, and pin-level validation Implement and verify Clock DFT / clock test methodologies Perform DFT DRC and testability checks Support JTAG, Boundary Scan, and IJTAG implementation and validation Perform gate-level simulation and debug of DFT test modes Work closely with RTL, design verification, physical design, and silicon teams Develop automation scripts using Tcl, Python, or Perl Analyze test coverage and improve

DFT/ATPG

quality and efficiency Required Qualifications 5+ years of hands-on

DFT/ATPG

experience Strong experience with ASIC/SoC DFT Hands-on experience with ATPG pattern generation, analysis, and debug Strong knowledge of scan insertion and scan-based testing Experience with MBIST / Memory BIST Experience with Clock

DFT / OCC

/ at-speed testing Knowledge of DFT DRC and testability Strong understanding of digital design and RTL Experience with industry-standard

DFT/ATPG EDA

tools such as Siemens Tessent, Synopsys TetraMAX/DFT Compiler, or Cadence Modus Strong debugging and analytical skills Excellent communication and teamwork skills Preferred Skills

JTAG / IEEE 1149.1 IJTAG / IEEE 1687

Boundary Scan Scan Compression / EDT Cell-Aware

ATPG LBIST

Gate-Level SDF Simulation Test-mode constraints / SDC Tcl / Python / Perl automation Silicon bring-up and post-silicon debug

Pay:

$90,600.00 - $110,000.00 per year

Work Location:

In person