design verification engineer.cedar rapids, iowaposted 1 day ago job detailssummary$61 - $76.32 per hourcontractbachelor degreecategorycomputer and mathematical occupations reference 1361610 job details job summary: Join Our Client to verify cutting-edge avionics and shape the future of flight to redefine aerospace! We need pros with a STEM degree, 5+ yrs' experience, SystemVerilog/UVM, and

DO-254 DAL A

expertise.

location:

Cedar Rapids, Iowa job type: Contract salary: $61.00 - 76.32 per hour work hours: 7am to 3pm education: Bachelors responsibilities: Architect and implement advanced constrained-random and directed verification environments (UVM/SystemVerilog) for complex ASIC, FPGA, and SoPC airborne hardware for Our Client.

Drive requirements-based and coverage-driven verification, generating

DO-254 DAL A

artifacts and supporting FAA SOI audits for Airborne Electronic Hardware.

Conduct functional, code, and assertion coverage analysis, CDC analysis, and regression automation to ensure robust, high-quality digital hardware.

Partner with digital design, systems, and certification teams while estimating verification scope, supporting bids, and communicating across program teams for Our Client.

Mentor junior engineers and recommend workflow and tool enhancements to drive continuous improvement across Our Client's engineering organization.

qualifications:

Bachelor's degree in a STEM discipline with a minimum of 5 years of prior relevant design verification experience, or an Advanced Degree in a related field. Hands-on experience developing testbenches and verification environments in SystemVerilog, VHDL, or Verilog using simulation tools such as Questasim, Vivado, or Libero. Strong understanding of common digital interfaces, timing constraints, clock domain crossings, and scripting languages such as Python, C/C++, or Linux shell.

skills:

in design,ASIC,C/C++,code coverage,linting,networking technologies,Networking solutions,digital hardware,Ethernet,FPGA,hardware test,PCIe,Perl,Python,scripting languages,SystemVerilog,systems engineers,Linux shell,VHDL,Verilog,Vivado,Communicate effectively,Ability to work independently,architecture,audits,automation,continuous improvement,design assurance,interface specifications,Design Verification,DO 254,electronic hardware,coverage analysis,functional coverage,I2C,Avionics,Mathematics,safety critical,Mentor,program management,project engineering,quantification,RFPs,requirements capture,risk management,mitigation planning,simulation,simulation tools

Equal Opportunity Employer:

Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com. Pay offered to a successful candidate will be based on several factors including the candidate's education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad offers a comprehensive benefits package, including: medical, prescription, dental, vision, AD&D, and life insurance offerings, short-term disability, and a 401K plan (all benefits are based on eligibility). This posting is open for thirty (30) days.