Find Jobs
Find Jobs Near You – Available Work in Your Location
Skip to job details
A
Apple
Emulation Verification Engineer
Career Insights for Verification Engineer
See where this job fits in the broader career landscape. Knowing your career path helps you see what's possible from here.
Scorecard
Based on Oregon data
Review key factors to help you decide if this role fits your goals. How is this calculated?
What they do
A Verification Engineer is responsible for ensuring that a product meets its specifications and requirements. Designs methods to test products, identify bugs in software products, and communicates with cross-functional teams, ensuring product development procedures and outcomes meets regulations. Primary objective is to verify that the system functions correctly and reliably according to its design and intended purpose.
$139,186 / year median in Oregon
Job Description
Imagine what you'll do at Apple! New insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what we could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. At Apple, we're passionate about changing the world! We have a critical impact on getting high quality functional products to millions of customers quickly! We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at the center of a chip design effort collaborating with Architecture, Design and SW teams! Description As a member of the Emulation verification team, we play a key role in using Emulation for verification of large SoCs. The overall work will involve porting the design onto the Palladium platform, followed by completing the detailed Emulation testplans.
- Collaborate closely with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platform
- Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
- Prepare and complete the test plan and perform reviews with the multi-functional teams
- Perform low power testing on emulation platform
- Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM
- Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a huge plus Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow Proven design verification skills Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions Experience with System Verilog verification environments including