PCIe ASIC Design EngineerPosition OverviewWe are seeking a results-driven PCIe ASIC Design Engineer to join our silicon engineering team. The role focuses on architecting and implementing PCIe interfaces and associated ASIC blocks from RTL through silicon bring-up, ensuring high-performance, low-latency connectivity for next-generation systems. The successful candidate will collaborate closely with SoC, PHY and verification teams to deliver robust, silicon-quality PCIe solutions and support system-level integration.

Key ResponsibilitiesDesign and implement PCIe interfaces and related ASIC logic (RTL) to meet performance, area, and power targets.

Collaborate with architecture, PHY, MAC and system teams to define interface requirements and ensure seamless SoC integration.

Develop and review micro-architecture and detailed design documentation, including TLP/DLL/flow control where applicable.

Perform RTL coding, linting, functional simulation and cycle-accurate modeling; drive synthesis and timing closure with focus on hold/setup constraints.

Work closely with verification teams to plan and execute verification strategies using simulation (VCS, Questa), emulation (HAPS, Palladium, Zebu) and FPGA prototypes.

Lead silicon bring-up activities: debug silicon bring-up issues, characterize PHY/retimer/switch behavior and collaborate with board and system engineers on validation.

Analyze signal integrity and timing issues related to high-speed interfaces (PCIe, CXL, CCIX) and support retimer and switch integration where required.

Participate in cross-functional design reviews, provide mentorship to junior engineers and drive design-for-test, power optimization and manufacturability improvements.

Develop scripts and automation (Tcl, Python, Perl) to accelerate design and verification flows, and manage release artifacts and ECOs.

Support customer-facing debug and performance tuning activities; provide clear technical documentation and handover packages for production and field support.

QualificationsBachelors or Masters degree in Electrical Engineering, Computer Engineering or related field.5+ years of ASIC design experience with a strong emphasis on PCIe interface design and silicon bring-up.

Proven RTL design skills in SystemVerilog or VHDL and experience with synthesis flows, STA and timing closure.

Hands-on experience with PCIe protocol details (TLP, DLL, flow control) and practical knowledge of PHY and MAC interactions.

Experience with verification tools and methodologies including VCS and Questa; familiarity with emulation platforms (Zebu, Palladium, HAPS) is highly desirable.

Experience with retimers, switches, and high-speed interconnects; familiarity with CXL and CCIX is a plus.

Strong debug skills using signal-level tools and lab equipment; experience in board bring-up and characterization.

Proficiency in scripting and automation (Python, Tcl) and experience with version control and CI flows.

Excellent communication, teamwork and problem-solving skills; ability to work in a fast-paced, cross-functional environment.

Nice-to-have:

exposure to SoC design flows, AI/ML workloads optimization on interconnects, and experience working in verification-heavy environments.

BenefitsCompetitive compEquityFull health insurance benefits (medical, dental, vision)401k w/matchPTO/Paid holidays/OTOStrong growth/advancementFSA/HSALife insurancePer insuranceMuch more!