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US Tech Solutions
Verification Engineer 4- #26-22322
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What they do
A Verification Engineer is responsible for ensuring that a product meets its specifications and requirements. Designs methods to test products, identify bugs in software products, and communicates with cross-functional teams, ensuring product development procedures and outcomes meets regulations. Primary objective is to verify that the system functions correctly and reliably according to its design and intended purpose.
$135,868 / year median in Texas
Job Description
$70-$80 per hour . By applying, you acknowledge that AI-assisted tools may be used during hiring. \#LI-AS140
AUSTIN, TX
ContractDuration:
12 months- Job Description
- + Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) + Strong proficiency in System Verilog Assertions (SVA) and formal property specification + Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis + Familiarity with scripting languages (TCL, Python, Perl) for flow automation + Extensive experience in design verification with a strong focus on formal verification + Expertise in System Verilog and UVM-based verification methodologies - Nice to have •
About US Tech Solutions:
- US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.
- US Tech Solutions is an Equal Opportunity Employer.
- All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran