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ML
Majestic Labs ai
AI SoC Architect Networking
Career Insights for Artificial Intelligence Engineer (General)
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What they do
An Artificial Intelligence Engineer develops, tests, and deploys artificial intelligence models. May work closely with data software engineers and data professionals to train and implement AI models into existing systems or develop new applications.
$160,491 / year median in California
Job Description
About Majestic Labs We're a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world's most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we're scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About The Position This is a highly technical and cross-functional role requiring deep expertise in SoC networking, high-speed interconnects, and protocol acceleration for AI. As a SOC System Network Architect for AI, you will lead the definition and architectural design of network engines and interconnect fabrics powering our custom AI servers. You will collaborate closely with silicon architecture, hardware design, firmware, and software teams to shape scale-up and scale-out networking topologies optimized for distributed AI workloads. Responsibilities Architect end-to-end SoC networking engines, SmartNIC/NIC architectures, and switch interface IPs for AI accelerators Define scale-up (intra-node) and scale-out (inter-node) network topologies Design hardware acceleration and offload engines for AI collective operations (e.g., AllReduce, AllGather, AllToAll) directly on the network fabric Optimize transport protocols (RoCEv2, custom RDMA engines, TCP/UDP offloads) and adaptive routing/congestion control algorithms (e.g., DCQCN) for synchronized AI traffic flows Drive performance modeling, cycle-accurate simulations, and traffic pattern analysis to evaluate architectural trade-offs across network fabrics Collaborate with ASIC design, silicon architecture, and AI software teams to define hardware/software interfaces, register abstractions, and programming models Produce high-quality network architecture specifications, interface documents, and lead cross-functional architecture reviews