Lead end-to-end AI system, memory, and hardware architecture, identifying cross-layer opportunities across workloads, runtimes, memory systems, and hardware. Develop architectural abstractions and mechanisms that connect AI model execution behavior with platform capabilities. Analyze emerging AI workloads, including computation, memory access, communication, data movement, bandwidth, latency, capacity, and power requirements. Drive pre-silicon architectural exploration, performance modeling, feasibility analysis, and implementation pathfinding for next-generation AI hardware. Evaluate trade-offs across performance, bandwidth, latency, power, thermal limits, silicon area, packaging, and total cost of ownership. Build analytical models, simulators, prototypes, and experimental systems to validate architectural hypotheses. Collaborate across research and product engineering, publish research, mentor technical contributors, and transfer promising concepts toward deployment. Doctorate in Computer Science, Computer Engineering, Electrical Engineering, or relevant field AND 6+ years related research experience OR Master's Degree in Computer Science, Computer Engineering, Electrical Engineering, or relevant field AND 7+ years related research experience OR Bachelor's Degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field AND 9+ years related research experience OR equivalent experience. Extensive experience in computer architecture, memory systems, silicon architecture, AI systems, platform design, or hardware/software co-design. Experience reasoning across workload behavior, system software, memory hierarchy, interconnects, and hardware architecture. Experience with pre-silicon architecture definition, modeling, feasibility analysis, or highly parallel accelerator-based systems. Record of technical innovation demonstrated through research, patents, publications, prototypes, architecture delivery, or product deployment. Experience with

DRAM, HBM, CXL, GPU

memory systems, host-memory interfaces, or high-bandwidth memory architectures. Experience with accelerator-attached memory, advanced packaging, 2.5D/3D integration, or high-speed scale-up interconnects. Experience analyzing large AI workloads such as LLM inference or training, mixture-of-experts routing, and KV-cache behavior. Experience developing performance models, cycle-accurate simulators, prototypes, or performance-analysis infrastructure. Experience translating new memory or hardware capabilities into measurable system-level improvements. Experience evaluating bandwidth, latency, capacity, locality, power, thermal, area, and data-movement trade-offs. Publication or patent record in computer architecture, systems, memory systems, AI infrastructure, or hardware platforms. Experience collaborating across research, pre-silicon design, and product engineering organizations.