EDA Engineer Mojo Vision Cupertino, CA Job Details Full-time $188,000 - $230,000 a year 20 hours ago Qualifications Schematics Tooling Semiconductor electronics Process improvement Electrical engineering Master's degree Digital circuit design Software development Electrical Engineering Full Job Description EDA Engineer Cupertino, CA / EDA Engineer / Full-Time Mojo Vision is pioneering a highly flexible, wafers-in, wafers-out micro-LED platform to unlock AI applications in multiple market segments. Built over the past decade by our world-class engineers, our system-level approach combines advanced 300mm silicon architecture with GaN-on-Silicon emitters, proprietary quantum dots, photodetectors, micro-lens arrays, and packaging to solve conventional trade-offs in size, brightness, bandwidth density, and power. Our scalable, manufacturing-ready approach enables breakthrough products such as next-generation optical interconnects and AI glasses. At Mojo, our team includes talented professionals with expertise in hardware, software, optics, photonics, electronics, chemistry, and applied physics. We are based in Cupertino, California and are backed by some of the world's leading technology investors.

Roles and Responsibilities:

Design Flow Development & Automation:

Developing and maintaining specialized software flows for Analog flows, front-end (RTL, simulation), and back-end (synthesis, place and route, timing) design stages.

CAD Methodology Improvement:

Evaluating and enhancing design methodologies to increase efficiency, such as implementing AI-driven design automation or customizing scripts in SKILL, Python, Tcl, or Perl to streamline repetitive tasks.

Tool Configuration and Support:

Installing, configuring, and troubleshooting Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, or Siemens-EDA to ensure they meet project-specific requirements.

Physical Verification & Sign-off:

Managing design rule checks (DRC), layout vs. schematic (LVS) verification, and parasitic extraction to ensure the chip is manufacturable (tape-out ready).

PDK and Library Management:

Maintaining Process Design Kits (PDKs) and standard cell libraries provided by foundries to ensure accurate simulation and layout.

Qualifications:

BSEE or MSEE, and 10+ years of experience in

EDA Tools:

Expertise in major tools like Cadence, Synopsys (Virtuoso, Encounter, etc.).

Scripting:

Proficiency in SKILL, Python, Tcl, Perl for automation.

Physical Design:

Experience with DRC (Design Rule Check), LVS (Layout Versus Schematic), P&R (Place & Route), and related flows.

Circuit Design:

Understanding of digital and analog IC design principles.

Semiconductor Process:

Knowledge of fabrication processes and Device Physics.

Programming:

Familiarity with SKILL and hardware description languages (e.g., Verilog/VHDL) is often required. Experience in full-chip or block-level physical design. Developing/supporting PDKs (Process Design Kits) and PCELLs.

Valuable Additional Qualifications:

Experience with leading and mentoring layout team members

Preferred Skills:

Strong interpersonal and problem-solving skills Prior experience bringing communication products to mass production

Salary Range:

$188K-$230

K Level:

Principal Engineer Pay:

$188,000.00 - $230,000.00 per year

Work Location:

In person