Required Skills:

Expert-level verification engineer with strong SystemVerilog and/ or UVM experience or FPGA verification in lab testing and/or Hardware FPGA design verification testing Experience with design on Xilinx products would be a strong plus expected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team.

Core Responsibilities RTL Design & Simulation:

Develop code and testbenches using VHDL, Verilog, and SystemVerilog.

Verification:

Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.

Hardware Lifecycle:

Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. [1]

Key Qualifications Experience:

Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).

Education:

Degree in a STEM (Science, Technology, Engineering, Mathematics) field.